Freescale Semiconductor /MKW21Z4 /XCVR_TSM_REGS /TIMING18

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIMING18

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SY_DIVN_EN_TX_HI0SY_DIVN_EN_TX_LO0SY_DIVN_EN_RX_HI0SY_DIVN_EN_RX_LO

Description

TSM_TIMING18

Fields

SY_DIVN_EN_TX_HI

Assertion time setting for SY_DIVN_EN (TX)

SY_DIVN_EN_TX_LO

De-assertion time setting for SY_DIVN_EN (TX)

SY_DIVN_EN_RX_HI

Assertion time setting for SY_DIVN_EN (RX)

SY_DIVN_EN_RX_LO

De-assertion time setting for SY_DIVN_EN (RX)

Links

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